This invention is in the field of integrated circuits, and is more specifically directed to oscillator circuits, such as may be used in clock generation and clock recovery in very large scale integrated (VLSI) logic circuits such as microprocessors and digital signal processors.
As is fundamental in the art, the operating clock rates of modern VLSI circuits, such as microprocessors and digital signal processors (DSPs), have increased greatly over recent years. These clock rates, now up to on the order of hundreds of MHz, and the corresponding increase in the number of operations that can be performed over time by the VLSI circuits, have provided dramatic increases in the functionality of electronic computing systems, including mobile, battery-powered, systems such as notebook computers, wireless telephones, and the like. In order to provide such high speed functionality, functions such as on-chip clock generation and clock recovery (i.e., generation of timing information from serial bitstreams) must of course operate at these high frequencies.
As related to clock generation, the increase in clock frequencies has in turn made the timing constraints for communication among the various integrated circuits more stringent. Particularly in systems that utilize synchronous operation and data communication among multiple integrated circuits, the timing skew between external system clocks and the internal clocks that control the operation of the integrated circuits must be reduced to very small margins.
Conventional systems generally utilize analog PLLs for on-chip generation and synchronization of internal clock signals from system reference clocks. Typical analog PLLs include a phase detector that compares the phase relationship of the reference clock to an internal clock, a charge pump and loop filter for setting an analog voltage corresponding to this phase relationship, and a voltage-controlled oscillator (VCO) for generating an output clock signal in response to the analog voltage from the charge pump and loop filter. In recent years, digital phase detectors have been used in on-chip PLLs in combination with the analog charge pump and filter, and the analog VCO; such PLLs have been referred to as “digital”, but of course in reality these PLLs are hybrid digital and analog circuits.
Recently, efforts have been made toward the development of fully digital PLLs. In combination with a digital phase detector, fully digital PLLs include a digital loop filter instead of the traditional analog filter, and include a digitally-controlled oscillator instead of the voltage controlled oscillator. In theory, these fully digital PLLs have several advantages over their analog counterparts. Firstly, digital logic exhibits much better noise immunity than analog circuitry. Secondly, analog components are vulnerable to DC offset and drift phenomena that are not present in equivalent digital implementations. Furthermore, the loop dynamics of analog PLLs are quite sensitive to process technology scaling, whereas the behavior of digital logic remains unchanged with scaling; this requires much more significant redesign effort to migrate analog PLLs to a new technology node than is required for digital PLLs.
Moreover, power dissipation is of extreme concern for portable, battery-powered, computing systems, as power dissipation relates directly to battery life. As a result, many manufacturers are reducing the power supply voltage requirements of the integrated circuits, particularly those that are specially adapted for portable computing systems, to reduce the power consumed by these devices. It has been observed, however, that a reduction in the power supply voltage applied to analog circuitry, such as analog or hybrid PLLs, does not necessarily reduce the power dissipated by these circuits; in some cases, aggressive voltage scaling has been observed to increase the power dissipated by analog circuits. Additionally, reduction in the power supply voltage to analog circuits renders the design of robust circuits much more difficult, given the reduced available “headroom” for the circuits.
For these reasons, PLLs in which digital techniques are used in not only the phase detector, but also in the loop filter and the controllable oscillator, are very attractive to designers. In particular, and as noted above, the implementation of fully digital PLLs to include a digitally-controlled oscillator (DCO), which is an oscillator that operates at a frequency controlled by the value of a digital control word applied thereto, has become especially attractive.
As is known in the art, high frequency circuits other than clock generation circuits also may benefit from the implementation of an all-digital PLL. For example, as noted above, the function of clock recovery (i.e., the extraction of timing information and synchronization from a serial bitstream) is common in effecting high-frequency data communication among integrated circuits and systems. It is, of course, desirable to communicate data at as high a frequency as possible, and as such the frequencies at which clock recovery circuitry are to operate are ever-increasing. Furthermore, considering that communication is a primary function in many battery-powered systems, such as wireless telephones, wireless modems in portable computers, and the like, it is desirable to reduce power dissipation and, consequently, the supply voltage required to implement clock recovery circuits, along with increasing the frequency of operation thereof. As such, many of the advantages provided by fully digital PLLs and the DCOs contained therein are also beneficial to clock recovery circuits, as well as other applications in modern integrated circuits. It should also be noted that the utility of the DCO is not limited to PLL applications. In fact, it is contemplated that any application requiring a frequency-programmable oscillator has the potential to benefit from an efficient implementation of a DCO.
The fundamental function of a DCO is to provide an output waveform, typically in the form of a square wave, which has a frequency of oscillation fDco that is a function of a digital input word D, as follows:fDCO=f(D)=f(dn-12n-1+dn-22n-2+ . . . +d 121+d020)Typically, the DCO transfer function f(·) is defined so that either the frequency fDCO or the period of oscillation TDCO is linear with D, generally with an offset. For example, a DCO transfer function that is linear in frequency is typically expressed as:f(D)=foffset+D·fstepwhere foffset is a constant offset frequency and fstep is the frequency quantization step. Similarly, a DCO transfer function that is linear in period is typically expressed as:       T    ⁢          (      D      )        =            1              f        ⁢                  (          D          )                      =                  T        offset            +              D        ·                  T          step                    where Toffset is a constant offset period and Tstep is the period quantization step. It is of course evident that, since the DCO period T(D) is a function of a quantized digital input D, the DCO cannot generate a continuous range of frequencies, but rather produces a finite number of discrete frequencies. In this regard, since the quantization granularity of the DCO period sets some fundamental limits on the achievable jitter of a PLL, it is of course desirable to have a fairly small quantization step size (e.g., period quantization step Tstep).
One common type of conventional DCO includes a high-frequency oscillator in combination with a programmable frequency divider. An example of this type of DCO is illustrated in FIG. 1a. In this example, programmable frequency divider 2 receives an n-bit digital word D which indicates the divisor value at which the frequency of the output signal HFCLK of high-frequency oscillator 4 is to be divided in generating the DCO output signal CLK. In this conventional arrangement, the period quantization step Tstep, and thus the lower bound of the timing jitter, is limited to the period of high-frequency oscillator 4. Low jitter operation thus requires oscillator 4 to operate at an extremely high frequency; for example, a 0.2 nsec step between periods requires high frequency oscillator 4 and programmable counter 2 to operate at 5 GHz.
Because of this limitation, other conventional DCO approaches directly synthesize a signal, rather than dividing down from a high frequency source. One example of a conventional direct-synthesis DCO is illustrated in FIG. 1b, which is arranged as a variable length ring oscillator. In this example, 2n delay stages 6 are connected in series, with lowest order stage 60 being an inverting stage and driving the output signal on line CLK. Decoder 8 decodes n-bit digital control word D into 2n control lines, each of which are operable to short out a corresponding stage 6, and one of which is asserted in response to the value of the digital control word D. The period of oscillation T is thus twice the sum of the delays of those delay stages 6 within the ring. For example, if the delay through each stage 6 is T6, in the case where D=0 such that only stage 60is in the ring, the period of oscillation T will equal 2T6; in the case where D=2n−1 (D is at its maximum), the period of oscillation T will equal 2(2n)T6, as all 2n stages 6 will be connected in the ring. In this conventional approach, the period quantization step (which sets a lower bound on the jitter) is thus 2T6, or twice the propagation delay of stage 6, which is typically an improvement over that of the conventional DCO of FIG. 1a, but which still may be too coarse for many applications. However, the integrated circuit chip area required for realization of the variable delay ring oscillator of FIG. 1b is substantial, considering that the number of stages 6 is exponential with the number of bits in the control word D and that typical delay stages can be quite complex, with some reported implementations requiring more than twenty transistors per stage. Furthermore, the complexity of decoder 8 is also exponential with n, itself requiring on the order of (n+6)2n unit-size transistors. The total complexity of the circuit is therefore relatively large, resulting in a chip area that varies with n by on the order of (n+30)2n. Accordingly, a high resolution DCO constructed in this fashion can occupy a tremendous amount of chip area.
Another known approach to implementation of a digital PLL is described in J. Dunning et al., “An All-Digital Phase-Locked Loop with 50-Cycle Lock Time Suitable for High-Performance Microprocessors”, J. Solid State Circ. (IEEE, April 1995), pp. 412-422. According to this conventional approach, the desired output frequency is directly synthesized through the operation of an eight-stage current-starved ring oscillator, one such stage illustrated in FIG. 1c, where each inverting delay stage includes a pull-up leg of parallel binary-weighted transistors 9, and a pull-down leg of parallel binary-weighted transistors 11. Each transistor 9i, 11i is turned on by a corresponding bit di (or its complement) of the control word d; switching transistors 9I, 11I are controlled by the state of line IN, and drive line OUT at their common drain node. While acceptable frequency resolution is provided according to this approach, the amount of integrated circuit chip area required for implementation of this PLL is extremely large. Since an NMOS transistor 11i weighted by a factor of 2i is generally realized as 2i minimum-size transistors 110 in parallel, the number of unit-size NMOS transistors 110 in a delay stage such as shown in FIG. 1c is 2(2n)−1. Assuming a PMOS transistor 9 to be twice the size of its corresponding NMOS transistors 11, the total number of unit-size transistors required to realize the delay stage of FIG. 1c may be considered as:2(2n)−1+2[2(2n)−1]=6(2n)−3For a DCO of this construction having eight delay stages, the area required for implementation will therefore vary with n by on the order of 48(2n).
By way of further background, another example of a conventional digitally-controlled oscillator is described in F. Lu, H. Samueli, J. Yuan, and C. Svensson, “A 700-MHz 24-b Pipelined Accumulator in 1.2-um CMOS for Applications as a Numerically Controlled Oscillator,” IEEE Journal of Solid-State Circuits, Vol. 28, No. 8 (IEEE, August 1993), pp. 878-886.